The disclosure relates to a data storage element for providing an output value based on an input signal, and to a signal processing method.
In various digital applications logical signals are transferred between different clock domains. For example, heterogeneous, asymmetric or asynchronous multicore processors are designed, which often use clock-domain crossing due to such asynchronous clock domains.
In conventional applications first-in-first-out, FIFO interfaces or asynchronous interfaces are used for data exchanges, which use serially coupled flip flops to avoid failure due to metastability. The number of such flip flops in such synchronizer means is inter alia dependent on clock frequency, a data rate and the used technology. For example in applications with clock frequencies over 200 MHz in 32 nm technology three cascaded flip flops are required, while for clock frequencies above 800 MHz the number of required flip flops may be at least five. Hence a special design and a greater area on an integrated circuit are needed for reducing a mean time between failures, MTBF, in such circuits.